The invention relates to a system for reducing noise on an add-in computer bus.
High resolution displays are typically driven by graphics controllers which may be located directly on computer motherboards to provide the best price/performance ratio or, alternatively, located on add-in boards such as video cards to provide expendability. The graphics controllers in turn are controlled by processors on the motherboards to provide a high resolution display capability. Typically, a first generation video card communicates with the processor via an Industry Standard Architecture (ISA) bus, while a newer video card may communicate with the processor via a faster Peripheral Component Interconnect (PCI) bus. However, even this improved data transfer rate is insufficient for certain graphical operations such as 3-D operations.
To improve the data transfer rate for graphic intensive operations, a new graphics bus known as an Advanced Graphic Port (AGP) bus has been specified. The AGP bus is more robust than the PCI bus since it is a bus which is dedicated to display operations. In contrast, the PCI bus shares its bandwidth with other devices connected to the PCI bus. Additionally, the AGP bus may double its bandwidth by transferring data on both rising and falling edges of the clock.
In addition to the faster clock speed and the dedicated graphics nature of the bus, the AGP bus increases its performance by providing an extra port for a graphics controller to access a shared system memory so that the controller can concurrently read texture information from a section of shared system memory while reading or writing Z-values and pixels from a local memory. Moreover, the AGP bus allows the computer's processor to write directly to the shared system memory when it needs to provide graphics data, commands or animated textures to the graphics device. These features increase the graphics display speed during a rendering of high resolution 3D scenes.
The AGP bus specifies a point-to-point bus which should only connect one AGP target device to one AGP master device. This restriction minimizes a degradation of the AGP bus signals as the AGP bus operates at a relatively high frequency. Many systems integrate AGP devices on their motherboards to optimize their price-performance ratio. However, a motherboard with both an integrated AGP device and an upgrade slot capable of receiving a second AGP device violates the point-to-point concept when the second AGP device is inserted into the upgrade slot. Thus, users can select from choices of (1) a cost-effective, but non-upgradable system with an AGP device integrated onto the motherboard, or (2) an upgradable computer system that incurs the extra cost associated with an AGP add-in board.